While an EPROM is an Electrically Programmable Read Only Memory device that is ultra-violet (UV) eraseable, a more recent non-volatile memory device has been developed called a FLASH EEPROM which is acronym for an Electrically Programmable and Electrically Bulk Eraseable Read Only Memory. The FLASH EEPROM differs from the EPROM in that it is electrically eraseable instead of UV eraseable, and differs from the standard EEPROM (Electronically Programmable and Electrically Eraseable Read Only Memory) in that the FLASH EEPROM is bulk eraseable whereas the standard EEPROM is byte eraseable. There are other differences between the three devices. Typically, an EPROM has the smallest cell size of the three, ranging between 10 to 60 square microns and hence is capable of high density, up to four megabits. An EEPROM, on the other hand, has the largest cell size of the three, ranging from 100 to 200 square microns and hence does not have a very high density. A FLASH EEPROM cell size currently is intermediate between the EPROM and standard EEPROM, ranging between 30 to 100 square microns, hence is capable of densities higher than that of a standard EEPROM. At the present stage of development, the electrical write and electrical erase cycling endurance of the FLASH EEPROM is less than that of the standard EEPROM, although progress is being made. The structures between the three devices originally were quite different, since the EPROM had a single transistor cell, while the EEPROM had two transistor cells. A FLASH EEPROM, on the other hand, has one merged transistor cell consisting of two transistors in series, a pass gate and a floating gate memory cell. Present trends in cell development are leading to fewer differences in structure between the three types of devices Thus the present invention, although specifically a FLASH EEPROM, can also be referred to as variants of the EPROM or standard EEPROM.
Traditionally, FLASH EEPROMS, EPROMs, EEPROMs, and EPALs have been implemented using a non-planar FAMOS technology. The non-planar technology, which does not use a cross-point cell structure with buried N+ bitlines, has several inherent problems First, because the bitlines used in the non-planar technology are not buried, they must be noncontinuous, each bitline covering only two or three cells. Consequently, the non-planar technology requires many contacts to be made to the large number of bitlines used therein. As a result of the numerous contacts required, the density of the non-planar technology is limited. Second, because of its uneven profile, the non-planar technology is not suited for stacked structures, in which one or more layers of circuitry are placed on top of the first memory array.
Many of the shortcomings of non-planar technology have been addressed in U.S. Pat. No. 4,597,060 to Mitchell, which describes a method of forming a planarized, cross-point FAMOS cell. The planar technology allows many cells to be disposed upon a continuous bitline, limited only by the sheet resistance and capacitance of the bitline, thereby reducing the number of contacts. The planar technology also provides for higher densities and stacked structures.
However, due to the relatively long bitlines, the speed of the device is reduced due to bitline resistance and bitline capacitance. Since speed is an important design criterion, the reduced speed represents a serious shortcoming in the art.
Therefore, a need has arisen for a planar FAMOS technology for use in EPROMs, EEPROMs, FLASH EEPROMs, EPALs, and other devices using similar memory structures, in which the speed of the device is increased.